1. Field of the Invention
The present invention relates generally to a semiconductor memory having a plurality of memory cells and a semiconductor memory write-in control device for controlling data written in the semiconductor memory, and more particularly to a semiconductor memory and a semiconductor memory write-in control device in which a plurality of storage value fixing memory cells functioning as those of a read only memory are arranged.
2. Description of Related Art
FIG. 6 is a view showing the configuration of a conventional memory cell. In FIG. 6, BL denotes a bit line. BL(inverted) denotes an inverted bit line set to a level opposite to that of the bit line BL. WL denotes a word line set to a high level or a low level according to an address signal. INV1 and INV2 indicate a pair of inverters cross-connected to each other so as to connect an input end of one inverter to an output end of the other inverter. T1 and T2 indicate a pair of n-channel metal-oxide-semiconductor (MOS) transistors connected to both the bit line BL and the inverted bit line BL(inverted) respectively. An output end of the inverter INV1 is connected to the transistor T1, and an output end of the inverter INV2 is connected to the transistor T2. The word line WL is connected to gates of the transistors T1 and T2. When the word line WL is set to the high level, the transistors. T1 and T2 are turned on. A conventional memory cell (MC) 10 is composed of the transistors T1 and T2 and the inverters INV1 and INV2.
FIG. 7 is a view showing the configuration of a conventional random access memory (RAM) representing a conventional semiconductor memory. In FIG. 7, S11 denotes a read/write request signal output from a central processing unit (CPU) not shown. In a data read operation, the read/write request signal S11 is output as a read-out request signal set to the low level. In a data write operation, the read/write request signal S11 is output as a write-in request signal set to the high level. S12 denotes an address signal output from the CPU. DB(O) to DB(7) denote data buses respectively. 10 indicates each of the plurality of conventional memory cells (MC) placed in a memory cell array. 11 indicates a read-write control circuit having both a read-out control circuit such as a sense amplifier (SA) and a write-in control circuit (WC). The pair of bit lines BL and BL(inverted) connected to each read-write control circuit 11 are set to levels opposite to each other in the write-in control circuit (WC) according to a value of bit data transmitted through the corresponding data bus DB in response to the write-in request signal S11. Bit data corresponding to different levels of the pair of bit lines BL and BL(inverted) connected to each read-write control circuit 11 is amplified in the read-out control circuit (SA) in response to the read-out request signal S11 and is output through the corresponding data bus DB. 12 indicates an address decoder (DEC) for receiving the address signal S12, selecting one word line WL connected to the memory cells 10 placed on a row of the memory cell array according to the address signal S12 and setting the selected word line WL to the high level. The conventional RAM shown in FIG. 7 has a plurality of memory cells 10 shown in FIG. 6 as basic memory cells (or read/write memory cells).
Next, an operation of the conventional RAM will be described below.
In a data write-in operation for one memory cell 10, a address signal S12 indicating a write-in address is transmitted from the CPU to the address decoder 12, one word line WL connected to the memory cell 10, in which bit data is planned to be written, is set to the high level according to the address signal S12. Therefore, as shown in FIG. 6, the transistors T1 and T2 of the memory cell 10 are turned on, and the memory cell 10 is electrically connected to both the corresponding bit line BL and the corresponding inverted bit line BL(inverted). Also, the write-in control circuit WC of the read-write control unit 11 connected to both the bit line BL and the inverted bit line BL(inverted) is operated in response to a write-in request signal S11, bit data transmitted from the outside through the corresponding data bus DB is written in the memory cell 10 through the write-in control circuit WC of the read-write control unit 11 and the bit line BL and the inverted bit line BL(inverted). In detail, the bit line BL is set to a first bit level (high or low level) according to the bit data, the inverted bit line BL(inverted) is set to a second bit level (low or high level) according to the bit data, the input end of the inverter INV2 is equalized to the first bit level of the bit line BL through the transistor T1, the input end of the inverter INV1 is equalized to the second bit level of the inverted bit line BL(inverted) through the transistor T2.
Also, in a data read-out operation for one memory cell 10, an address signal S12 indicating a read-out address is transmitted from the CPU to the address decoder 12, one word line WL connected to the memory cell 10, from which bit data is planned to be read out, is set to the high level according to the address signal S12. Therefore, the transistors T1 and T2 of the memory cell 10 are turned on, and the memory cell 10 is electrically connected to both the corresponding bit line BL and the corresponding inverted bit line BL(inverted), the bit line BL is equalized to a level of the output end of the inverter INV1, and the inverted bit line BL(inverted) is equalized to a level of the output end of the inverter INV2. Also, the read-out control circuit SA of the read-write control unit 11 connected to both the bit line BL and the inverted bit line BL(inverted) is operated in response to a read-out request signal S11, the levels of both the bit line BL and the inverted bit line BL(inverted) are amplified in the read-out control circuit SA to produce bit data, and the bit data is output as bit data stored in the memory cell 10 to the outside through the corresponding data bus DB.
FIG. 8A is a view showing the configuration of a conventional large scale integration circuit (LSI) manufactured before the determination of preset data and/or preset program codes, and FIG. 8B is a view showing the configuration of the conventional LSI manufactured after the determination of preset data and/or preset program codes. In FIG. 8A and FIG. 8B, 14 indicates a CPU. 15 indicates a RAM. 13 indicates an LSI having the RAM 15 and the CPU 14. 16 indicates an external memory placed at the outside of the LSI 13. 17 indicates a mask type read only memory (ROM). The RAM 15 and the mask type ROM 17 are operated under the control of the CPU 14. The external memory 16 is connected to the RAM 15. The RAM 15 has the same configuration as that of the conventional RAM shown in FIG. 7.
In an LSI having a RAM and a CPU such as a logic circuit, the onboard RAM is used as a memory for storing data and/or program codes required by an onboard CPU. However, because the RAM denotes a volatile memory, when an electric power supplied to the RAM is stopped, data and/or program codes stored in the RAM are undesirably lost. Therefore, it is required to store preset data and/or preset program codes (for example, a boot program or a self-diagnosis program) required by the onboard CPU to a ROM.
Also, in cases where an apparatus using an LSI is developed for the purpose of the mass production of the apparatus, the apparatus is made many times on an experimental basis, and the performance of the apparatus is tested each time the apparatus is made. In this case, the specification of the LSI is revised each time the apparatus is made on an experimental basis, and it is required to change data and/or program codes preset in the LSI in compliance with the revision of the specification of the LSI. Assuming that preset data and/or preset program codes are stored in a mask type ROM of the LSI before the final determination of the preset data and/or the preset program codes, it is required to replace the mask type ROM with another one each time the specification of the LSI is revised, and it takes a long time and a high cost to develop the apparatus. To prevent this problem, before the final determination of the preset data and/or the preset program codes, in other words, during the test operation of the apparatus made on an experimental basis, as shown in FIG. 8A, the RAM 15 is placed in the LSI 13, and the external memory 16 connected to the RAM 15 is placed outside the LSI 13. When electric power is provided to the LSI 13, data and/or program codes stored in the external memory 16 are transferred to the RAM 15 to preset the data and/or the program codes to the RAM 15. The external memory 16 is, for example, formed of a flash memory, and data can be rewritten in both the external memory 16 and the RAM 15. Therefore, each time it is required to revise the preset data and/or the preset program codes written in the RAM 15, the preset data and/or the preset program codes stored in the external memory 16 are rewritten, and the rewritten data and/or the rewritten program codes are transferred from the external memory 16 to the RAM 15 to rewrite the preset data and/or the preset program codes stored in the RAM 15. After the preset data and/or the preset program codes are finally determined, as shown in FIG. 8B, the external memory 16 is disconnected from the LSI 13, the mask type ROM 17 is manufactured so as to store the preset data and/or the preset program codes finally determined, and the RAM 15 of the LSI 13 is replaced with the mask type ROM 17 having the preset data and/or the preset program codes finally determined.
This method of replacing the RAM 15 with the mask type ROM 17 is used in cases where the preset data and/or the preset program codes are stored in all areas of the RAM 15.
Also, in a general RAM having a plurality of memory cells, because each inverter of one memory cell is composed of two transistors, six transistors are, for example, required to store a piece of bit information in the memory cell. In contrast, only one transistor is required to store a piece of bit information in a general ROM. Therefore, a size of the mask type ROM 17 can be considerably smaller than that of the RAM 15 to store the preset data and/or the preset codes, a die size of the LSI 13 can be reduced by using the mask type ROM 17 in place of the RAM 15, and the manufacturing cost of the LSI 13 can be reduced.
Also, in cases where an LSI having a RAM and not having a mask type ROM is used, an external memory having the preset data and/or the preset program codes finally determined is necessarily required. However, no external memory is required of the LSI 13 by storing the preset data and/or the preset program codes finally determined in the mask type ROM 17. Therefore, the LSI 13 can be easily arranged in an apparatus using the LSI 13.
However, because the conventional LSI shown in FIG. 8A and FIG. 8B has the above-described configuration, the preset data and/or the preset program codes finally determined by using the RAM 15 are stored in the mask type ROM 17, and the LSI 13 is finally manufactured by replacing the RAM 15 with the mask type ROM 17. In this case, the memory performance of the mask type ROM 17 such as data read rate and consumed current differs from those of the RAM 15. Also, because the layout of elements of the LSI 13 is changed due to the replacement of the RAM 15 with the mask type ROM 17, the characteristics of the LSI 13 are changed due to the replacement of the RAM 15 with the mask type ROM 17. Therefore, a problem has arisen that it is required to again estimate the performance of the apparatus using the LSI 13 after the final determination of the preset data and/or the preset program codes.
Next, an LSI not required to again estimate the performance of an apparatus using the LSI after the final determination of the preset data and/or the preset program codes will be described below.
FIG. 9A is a view showing the configuration of another conventional LSI manufactured before the determination of preset data and/or preset program codes, and FIG. 9B is a view showing the configuration of the conventional LSI manufactured after the determination of preset data and/or preset program codes. The constituent elements, which are the same as those shown in FIG. 8A or FIG. 8B, are indicated by the same reference numerals as those of the constituent elements shown in FIG. 8A or FIG. 8B, and additional description of those constituent elements is omitted. In the conventional LSI 13 shown in FIG. 9A, the mask type ROM 17 not yet having data or program codes is arranged with the RAM 15. When a switch is set to a first position, the RAM 15 is connected to the external memory 16 through the switch. Also, when the switch is set to a second position, the RAM 15 is disconnected from the external memory 16 but is connected to the ROM 17 through the switch.
Before the final determination of the preset data and/or the preset program codes, in other words, during the test operation of the apparatus made on an experimental basis, in the same manner as the LSI shown in FIG. 8A, the switch is set to the first position, and data and/or program codes stored in the external memory 16 are transferred to the RAM 15 to store preset data and/or-preset program codes to the RAM 15 when electric power is provided to the LSI 13. After the preset data and/or the preset program codes are finally determined, a wiring operation is performed for the mask type ROM 17 of the LSI 13 to write the preset data and/or the preset program codes finally determined in the mask type ROM 17, the switch is changed to the second position to disconnect the external memory 16 from the RAM 15, and the external memory 16 is removed. Therefore, the conventional LSI shown in FIG. 9B is obtained.
This method of arranging both the RAM 15 and the mask type ROM 17 in the LSI 13 is used in cases where pieces of data stored in all areas of the RAM 15 are not replaced with those of the mask type ROM 17. For example, in case of the RAM 15 having a memory capacity of 1.024 MB, the preset data and/or the preset program codes finally determined are stored in an area of 512 KB in the RAM 15, and pieces of data are written in or read out from an area of the other 512 KB in the RAM 15 during the operation of the LSI 13. Therefore, the function of the RAM 15 can be used in the LSI 13.
In the conventional LSI 13 shown in FIG. 9B, when the CPU 14 requires the preset data and/or the preset program codes finally determined, the preset data and/or the preset program codes stored in the mask type ROM 17 are transferred to the CPU 14 through the RAM 15. Therefore, the memory performance of the RAM 15 for the CPU 14 after the final determination of the preset data and/or the preset program codes is substantially the same as that before the final determination of the preset data and/or the preset program codes, and the layout of elements of the LSI 13 is not changed. Therefore, it is not required to again estimate the performance of the apparatus using the LSI 13 after the final determination of the preset data and/or the preset program codes.
However, because the conventional LSI shown in FIG. 9 has the above-described configuration, the mask type ROM 17 is arranged in the LSI 13 only to transfer the preset data and/or the preset program codes to the RAM 15. Therefore, another problem has arisen that the die size of the LSI 13 is enlarged, and the manufacturing cost of the LSI 13 is increased.
Also, the manufacturing cost of the mask type ROM 17 required to store the preset data and/or the preset program codes is high, investment in plant and equipment for the manufacturing of the mask type ROM 17 is high, and it takes a lot of time to manufacture the mask type ROM 17. Therefore, another problem has arisen that the manufacturing of a large number of mask type ROMs is required to reduce the manufacturing cost of each mask type ROM.
Another prior art will be described below.
A memory cell array and a semiconductor memory are disclosed in Published Unexamined Japanese Patent Application No. H05-314776 (1993). In this memory cell array of the semiconductor device, a part of a memory cell array is formed to memory cells having an unwritable fixed storage value to reduce an occupancy area of both a RAM and a ROM related to a semiconductor memory. However, because no inverter is used in the memory cell having an unwritable fixed storage value, the memory characteristics such as a data read-out time in the memory cell having an unwritable fixed storage value differs from those in the memory cell having a writable storage value. Therefore, even though the preset data and/or the preset program codes are determined by using the semiconductor memory having only the memory cells of writable storage values, it is required to again estimate the memory characteristics of the semiconductor memory having the memory cells of writable storage values and the memory cells of unwritable fixed storage values.
A main object of the present invention is to provide, with due consideration to the drawbacks of the conventional semiconductor memory, a semiconductor memory and a semiconductor memory writing-in control device in which the increase of a die size is prevented without changing characteristics of the semiconductor memory after the determination of preset data or a preset program code.
A subordinate object is also achieved by the provision of a semiconductor memory and a semiconductor memory writing-in control device in which the increase of a consumed current is prevented in the writing of data in the semiconductor memory.
A semiconductor memory includes a storage value fixing memory cell having a first inverter, a second inverter, a first transistor and a second transistor. An input end of the first inverter is connected to a low electric potential terminal or is connected to a high electric potential terminal. An input end of the second inverter is set to a level opposite to that of the input end of the first inverter. The first transistor is turned on according to a first word level of a word line to set a first bit line to a first bit level opposite to a level of the input end of the first inverter. The second transistor is turned on according to the first level of the word line to set a second bit line to a second bit level opposite to a level of the input end of the second inverter.
Therefore, characteristics of the semiconductor memory are not changed even though a read/write memory cell of the semiconductor memory is changed to the storage value fixing memory cell after the determination of preset data or a preset program code to store the preset data or the preset program code in the storage value fixing memory cell. Accordingly, the increase of a die size of the semiconductor memory can be prevented without changing characteristics of the semiconductor memory after the determination of the preset data or the preset program code.